抄録
RC-005
A2LUT: Abridged Adaptive LUT Architecture
○飯田全広・田浦　健・古賀正紘・井上万輝・尼崎太樹・末吉敏則（熊本大）
FPGAs are an important building block of reconfigurable systems and also have a cost-efficiency as an alternative to ASICs. However, FPGAs based on LUTs doesn't have enough area-efficiency. In this paper, we propose an abridged configuration memory logic cell named A2LUT that reduce the chip area and delay. Our approach is to investigate the appearance ratio of the logic functions in benchmarks. The experimental results show that the area in A2LUT is 16.8% smaller, the critical path delay is 21.9% smaller than 6-LUT. Moreover, we develop the prototype chip.